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MC100EL30 5V ECL Triple D Flip-Flop with Set and Reset
The MC100EL30 is a triple master-slave D flip-flop with differential outputs. Data enters the master latch when the clock input is LOW and transfers to the slave upon a positive transition on the clock input. In addition to a common Set input individual Reset inputs are provided for each flip flop. Both the Set and Reset inputs function asynchronous and overriding with respect to the clock inputs.
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1200 MHz Minimum Toggle Frequency 450 ps Typical Propagation Delays ESD Protection: >2 kV Human Body Model The 100 Series Contains Temperature Compensation. PECL Mode Operating Range: VCC = 4.2 V to 5.7 V with VEE = 0 V NECL Mode Operating Range: VCC = 0 V with VEE = -4.2 V to -5.7 V Internal Input 75 kW Pulldown Resistors Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test Moisture Sensitivity Level 1 For Additional Information, see Application Note AND8003/D Flammability Rating: UL 94 V-0 @ 0.125 in, Oxygen Index: 28 to 34 Transistor Count = 347 devices Pb-Free Packages are Available*
SO-20 WB DW SUFFIX CASE 751D
MARKING DIAGRAM*
20 100EL30 AWLYYWWG
1 A WL YY WW G = Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package
*For additional marking information, refer to Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet.
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
(c) Semiconductor Components Industries, LLC, 2006
October, 2006 - Rev. 5
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Publication Order Number: MC100EL30/D
MC100EL30
VCC Q0 Q0 VCC Q1 Q1 VCC Q2 Q2 VEE
20
19
18
17
16
15
14
13
12
11
Table 1. PIN DESCRIPTION
Pin D0-D2 R0-R2 CLK0-CLK2 S012 Q0-Q2; Q0-Q2 VCC VEE Function ECL Data Inputs ECL Reset Inputs ECL Clock Inputs ECL Common Set Input ECL Differential Data Outputs Positive Supply Negative Supply
Q S D
Q R S
Q D
Q R S
Q D
Q R
1
S012
2
D0
3
CLK0
4
R0
5
D1
6
CLK1
7
R1
8
D2
9
CLK2
10
R2
Warning: All VCC and VEE pins must be externally connected to Power Supply to guarantee proper operation.
Table 2. FUNCTION TABLE
R* L L H L H S* L L L H H D* L H X X X CLK* Z Z X X X Q L H L H Undef Q H L H L Undef
Figure 1. Logic Diagram and Pinout: 20-Lead SOIC (Top View)
Z = Low-to-High Transition X = Don't Care *Pin will default low when left open.
Table 3. MAXIMUM RATINGS
Symbol VCC VEE VI Iout TA Tstg qJA qJC Tsol Parameter PECL Mode Power Supply NECL Mode Power Supply PECL Mode Input Voltage NECL Mode Input Voltage Output Current Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction-to-Ambient) Thermal Resistance (Junction-to-Case) Wave Solder Pb Pb-Free 0 lfpm 500 lfpm Standard Board <2 to 3 sec @ 248C <2 to 3 sec @ 260C SOIC-20 SOIC-20 SOIC-20 Condition 1 VEE = 0 V VCC = 0 V VEE = 0 V VCC = 0 V Continuous Surge VI VCC VI VEE Condition 2 Rating 8 to 0 -8 to 0 6 to 0 -6 to 0 50 100 -40 to +85 -65 to +150 90 60 30 to 35 265 265 Unit V V V V mA mA C C C/W C/W C/W C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
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MC100EL30
Table 4. PECL DC CHARACTERISTICS VCC= 5.0 V; VEE= 0.0 V (Note 1)
-40C Symbol IEE VOH VOL VIH VIL IIH IIL Characteristic Power Supply Current Output HIGH Voltage (Note 2) Output LOW Voltage (Note 2) Input HIGH Voltage Input LOW Voltage Input HIGH Current Input LOW Current 0.5 3915 3170 3835 3190 Min Typ 55 3995 3305 Max 62 4120 3445 4120 3525 150 0.5 3975 3190 3835 3190 Min 25C Typ 55 4045 3295 Max 62 4120 3380 4120 3525 150 0.5 3975 3190 3835 3190 Min 85C Typ 55 4050 3295 Max 64 4120 3380 4120 3525 150 Unit mA mV mV mV mV mA mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 1. Input and output parameters vary 1:1 with VCC. VEE can vary +0.8 V / -0.5 V. 2. Outputs are terminated through a 50 W resistor to VCC - 2.0 V.
Table 5. NECL DC CHARACTERISTICS VCC= 0.0 V; VEE= -5.0 V (Note 3)
-40C Symbol IEE VOH VOL VIH VIL IIH IIL Characteristic Power Supply Current Output HIGH Voltage (Note 4) Output LOW Voltage (Note 4) Input HIGH Voltage Input LOW Voltage Input HIGH Current Input LOW Current 0.5 -1085 -1830 -1165 -1810 Min Typ 55 -1005 -1695 Max 62 -880 -1555 -880 -1475 150 0.5 -1025 -1810 -1165 -1810 Min 25C Typ 55 -955 -1705 Max 62 -880 -1620 -880 -1475 150 0.5 -1025 -1810 -1165 -1810 Min 85C Typ 55 -955 -1705 Max 64 -880 -1620 -880 -1475 150 Unit mA mV mV mV mV mA mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 3. Input and output parameters vary 1:1 with VCC. VEE can vary +0.8 V / -0.5 V. 4. Outputs are terminated through a 50 W resistor to VCC - 2.0 V.
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MC100EL30
Table 6. AC CHARACTERISTICS VCC= 5.0 V; VEE= 0.0 V or
-40C Symbol fmax tPLH tPHL tS tH tRR tPW Characteristic Maximum Toggle Frequency Propagation Delay to Output CLK, S, R Setup Time Hold Time Set/Reset Recovery Minimum Pulse Width CLK Set, Reset Min 1.0 550 150 200 400 400 650 TBD 280 550 280 0 100 200 800 Typ Max Min 1.2 570 150 200 400 400 650 TBD 450 550 280 0 100 200 820 VCC= 0.0 V; VEE= -5.0 V (Note 5) 25C Typ Max Min 1.2 590 150 200 400 400 650 TBD 550 0 100 200 840 85C Typ Max Unit GHz ps ps ps ps
tJITTER tr tf
Cycle-to-Cycle Jitter Output Rise/Fall Times Q (20% - 80%)
ps ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 5. VEE can vary +0.8 V / -0.5 V.
Q Driver Device Q
Zo = 50 W
D Receiver Device
Zo = 50 W 50 W 50 W
D
VTT VTT = VCC - 2.0 V
Figure 2. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020/D - Termination of ECL Logic Devices.)
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MC100EL30
ORDERING INFORMATION
Device MC100EL30DW MC100EL30DWG MC100EL30DWR2 MC100EL30DWR2G Package SOIC-20 SOIC-20 (Pb-Free) SOIC-20 SOIC-20 (Pb-Free) Package 38 Units / Rail 38 Units / Rail 1000 / Tape & Reel 1000 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
Resource Reference of Application Notes
AN1405/D AN1406/D AN1503/D AN1504/D AN1568/D AN1672/D AND8001/D AND8002/D AND8020/D AND8066/D AND8090/D - ECL Clock Distribution Techniques - Designing with PECL (ECL at +5.0 V) - ECLinPS I/O SPiCE Modeling Kit - Metastability and the ECLinPS Family - Interfacing Between LVDS and ECL - The ECL Translator Guide - Odd Number Counters Design - Marking and Date Codes - Termination of ECL Logic Devices - Interfacing with ECLinPS - AC Characteristics of ECL Devices
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MC100EL30
PACKAGE DIMENSIONS
SO-20 WB DW SUFFIX CASE 751D-05 ISSUE G
D
A
11 X 45 _
q
NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A A1 B C D E e H h L q MILLIMETERS MIN MAX 2.35 2.65 0.10 0.25 0.35 0.49 0.23 0.32 12.65 12.95 7.40 7.60 1.27 BSC 10.05 10.55 0.25 0.75 0.50 0.90 0_ 7_
H
M
B
M
20
10X
0.25
E
1 10
20X
B 0.25
M
B TA
S
B
S
A e
SEATING PLANE
h
18X
A1
T
C
ECLinPS are registered trademarks of Semiconductor Components Industries, LLC (SCILLC).
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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L
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MC100EL30/D

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